From the past, in order to stabilize power amplification characteristics against a power-supply-voltage variation, using a current-mirror-circuit-based bias method, the amount of current increase due to a channel length modulation effect of a source-grounded N-channel MOS transistor, which is biased by a constant current supplied by a constant current source, is detected by a current mirror circuit configured by a P-channel MOS transistor and a current mirror circuit configured by an N-channel MOS transistor (for example, refer to Patent Document 1 cited below).
Also from the past, in order to automatically correct deviation of bias due to a short channel effect of a MOSFET of a high-frequency power amplifier, there is technology which employs a current replicating transistor which has the same channel length and is fabricated by the same process as a power amplification transistor (for example, refer to Patent Document 2 cited below).
Furthermore, from the past, in order to correct deviation of bias due to a short channel effect of an FET of a high-frequency power amplifier, there is technology which provides, to a semiconductor chip of a high-frequency power amplifier, a pad coupled to a gate terminal of a bias transistor on an input side of a current mirror circuit, separately from a pad coupled to a gate terminal of a power amplification transistor on an output side of the current mirror circuit (for example, refer to Patent Document 3 cited below).
Patent Document
(Patent Document 1) Japanese Patent Laid-open No. 2005-150917.
(Patent Document 2) Japanese Patent Laid-open No. 2005-123861.
(Patent Document 3) Japanese Patent Laid-open No. 2005-020518.